The integrated circuit (IC) is one of the cornerstones of modern electronic devices; without ICs, many of the technologies that we take for granted would be practically impossible to implement. Reliability and performance in an IC is therefore of the utmost importance - a malfunctioning IC can result in complete failure of a system.
IC failure analysis is the process of taking one of these malfunctioning ICs and, through in-depth investigation, transforming it from a piece of scrap electronics into an invaluable source of actionable data for continuous improvement.
Our lab is equipped and staffed for IC failure analysis services aimed at fast turnaround and accurate results.
There are four main phases of every IC failure analysis project. The first phase is non-destructive testing, where tools like acoustic microscopy and x-ray imaging are applied to learn as much about the sample without permanently altering it in any way.
Next comes fault verification, where the analyst attempts to replicate the failing conditions reported by the customer; without confirming the failure, the project cannot continue, since there is no evidence to show that a defect even exists.
With the fault confirmed, the next phase is fault isolation, where the analyst identifies a site for an in-depth destructive physical analysis and examination. The analyst might use tools like photoemission microscopy (PEM), laser induced voltage alteration (LIVA), or thermal imaging to locate a defect; in other cases, microprobing of the die or a careful optical inspection of the die bonds might be sufficient to identify the root cause of failure.
Finally, destructive analysis and documentation serve as the culmination of all the data collection thus far: armed with the results from fault isolation testing, an analyst will perform deprocessing, a cross-section, or other destructive technique to reveal the defect in its entirety and identify its most likely cause.
Image collage showing bright-field (at top) and Differential Interference Contrast (at bottom) images of electrical overstress damage on an IC. The DIC images reveal contours corresponding to disruption of upper metal layers by the EOS event.
This device has seen better days - extensive damage to the bus metallization and lower layers implies massive current flow resulted in a device failure.
Photoemission Microscopy (PEM) image, showing an isolated site for further investigation.
Electron micrograph of a metal processing defect, which caused this sample to fail during initial testing.
IAL has an extensive breadth and depth of experience in many aspects of the modern semiconductor industry. From FPGAs to op-amps, silicon to III-V high frequency devices, mature processes to the most cutting-edge 22nm CMOS devices, we can produce valuable learning from almost any failing IC.
- Analyzing IC field failures
- Post-mortem of devices after reliability testing
- Identifying root cause of low-yield process
The primary limiting factor for any IC failure analysis project is the complexity of the setup needed to replicate the failing condition. Some failures only occur in very specific circumstances, or require specific supporting equipment in order to properly be put into a failing condition; while IAL can replicate many conditions using standard test equipment, more elaborate setups may require tools outside our normal scope of work. In these cases we are happy to work with you to determine the best course of action to successfully test your samples.