The culminating point of any semiconductor failure analysis job is the task of deprocessing the integrated circuit: removing the various layers of metal and oxide that make up a device until a defect or damage site is revealed. While, in theory, deprocessing seems straightforward, there are many potential pitfalls and nuances that must be accounted for; as such, IC failure analysis companies who can successfully offer IC deprocessing services on a wide range of parts are few and far between. Successful results hinge upon correctly identifying a process type and matching it with the proper set of techniques from an IC failure analysis engineers a comprehensive set of tools.
Relatively simple integrated circuits, or integrated circuits that are implemented on older processes, are often constructed using non-planar technologies. Failure analysis of semiconductors fabricated using this type of technology may often proceed fairly smoothly through the early stages of the project; the inherently lower density of these devices can make isolation a much simpler task than on more modern processes, where a defect might be completely covered with several layers of metal, obscured from the vast majority of inspection techniques. Deprocessing of these types of samples is usually accomplished using a variety of wet chemicals, alternately etching away metals and oxides in different alchemical concoctions until the defect site is exposed for inspection. Special care must be taken to limit the reactivity of the chemicals used so that excess material is not removed and the device retains enough of its inherent structure to facilitate a meaningful inspection. Without the proper forethought, all the circuitry on the device can float away and dissolve, leaving an analyst with a bare chunk of silicon (which, in some cases, maybe the desired result… but in others is disastrous).
Conversely, the modern, ultra-high-speed processors and other devices that most often spring to mind when one thinks of a “microchip” are fabricated using planar technologies that integrate many more layers of metal and more troublesome materials than their non-planar counterparts. The traditional approach to performing deprocessing for semiconductor failure analysis on these products is parallel lapping, a technique that uses an extremely fine abrasive to slowly slough away the metals and oxides of a device. The margin for error for this technique is very slim; many of the most cutting edge processes have spacings of roughly 1000 angstroms between layers (for comparison, a human hair is about one million angstroms thick, on average). Due to the nearly insurmountable difficulty of lapping such a device, some companies opt for a different approach, using chemicals to dissolve the silicon substrate of a device and inspect the circuitry from the backside. While this technique can successfully reveal defects at the diffusion and polysilicon layers of a device, a defect between layers of metal is often inaccessible using this approach.
Since deprocessing is such a critical part of any semiconductor failure analysis lab’s services, it is important to entrust critical defects only to those companies who have comprehensive experience with a wide range of process technologies. The more experience with deprocessing a company has at its disposal, the more likely they will be able to drive a successful analysis.