As mentioned in a previous article, the failure mode of an integrated circuit can, in the hands of a trained analyst, be pivotal in determining the course of analysis and successfully isolating a defect. Without understanding how a device malfunctions, it is nearly impossible to determine why – unless, of course, an analyst is blessed with an abundance of luck and a dearth of caution. For those who are not so happily gifted, a well-identified failure mode can save hours of time that would otherwise be spent digging through datalogs and schematics, hunched over a workbench illuminated by the faint green light of test equipment, hunting for any possible toehold to begin the analysis. While it is true that failure modes can be as unique and varied as the endless menagerie of integrated circuits they occur on, there are a handful of usual suspects that an analyst will see time and again over the course of their career.
One of the most common failure modes that an analyst will encounter is current leakage. Though this failure mode may be reported in several different ways – short-circuiting, excessive power consumption, short battery life – the final interpretation is the same. Since these failures involve current following paths on an integrated circuit that are normally non-conductive, they can in some cases be the most straightforward to find; as the anomalous current travels through the circuitry of the device, it can generate heat, photons of light, and other phenomena that can be detected with the various tools in an analyst’s repertoire. In devices returned from the field, this failure mode is often explained by electrical overstress (EOS), meaning that the device was subjected to some sort of voltage or current, like a static shock or a power surge, which caused permanent damage to its circuitry. Unfortunately, when an EOS event occurs on a device, any inherent defect that may have contributed to the failure is often consumed in the microscopic conflagration; as a result, a finding of electrical overstress is often the End Of the Story for a given device, with very little further data collection possible.
Another common failure mode is an open circuit condition. Though an open circuit may be caused by electrical overstress, fusing bond wires and metal traces, there are often more likely culprits. Devices exhibiting open circuits that are fresh from fabrication often exhibit processing defects like improperly drilled vias between metal layers, or misalignment of one layer of the die to the next. When returning from the field, the most likely cause for an open circuit is device wear out – this may simply be due to the device’s normal lifespan, or it may be due to an inherent process weakness causing early life failures. It is somewhat more difficult to find an open circuit – many of the tools used to find current leakage are nearly useless for finding an open. An analyst may choose instead to use an electron microscope and rely on the phenomenon of charge contrast – as the sample is bombarded with the microscope’s electron beam, parts of the circuit that have no path to an electrical ground will begin to charge and glow brightly, allowing the analyst to see where an electrical connection has failed.
Understanding the failure mode of an integrated circuit is the first step toward performing successful analysis. It is, however, only one step – after all, two devices with similar failure modes can wind up being very different, indeed.