IC Decapsulation - Exposing Semiconductor Devices for Analysis
In their final, packaged form, many of the secrets of integrated circuits are concealed from an analyst looking to uncover a failure. While techniques like x-ray and acoustic microscopy can penetrate the shroud of mold compound and FR4 that enfold the semiconductor die at the heart of a device and reveal some information, they rarely tell the whole story; to truly determine the root cause of failure, an analyst almost always needs to be able to examine the device directly. This examination may take many forms - optical or electron microscopy may reveal a defect site, or elemental analysis tools may identify contaminants causing corrosion or other issues - so the techniques used to expose the semiconductor die must take into account the potential failure mechanisms that are most likely for any given device. IC decapsulation is the process - part art, part science - of breaking in to these devices to discover what defects might lie within.
The most common technique used when performing IC decapsulation for a semiconductor failure analysis company is a wet chemical process. The mold compound on many products is susceptible to being dissolved by highly concentrated acids; since the vast majority of semiconductor die are protected by a passivation layer that is relatively impervious to these acids, there is little risk of damaging the device with this process, though a certain amount of care must be taken with unpassivated metals like aluminum bond pads to ensure they do not etch away along with the mold compound. Some specialized equipment will perform a wet decapsulation with pressurized streams of heated acid, focused by nonreactive gaskets onto the area of the IC package that an analyst wishes to remove. These decapsulation systems are limited by the selection of gaskets available to an analyst; without an appropriate gasket set, it is possible to either underexpose or overexpose the die, either of which can be problematic for further analysis. Many analysts prefer a more hands-on, low-tech approach to wet decapsulation: the sample is heated, and acid is trickled onto the device, one drop at a time; the dissolved product is rinsed away with a solvent, eventually exposing the die. With practice and good technique, an analyst using this approach can expose the semiconductor die without impacting any leadframe or underlying circuitry, so the device will function (mostly) identically to how it performed before decapsulation, allowing the use of isolation techniques like thermal imaging or photoemission.
Though wet decapsulation is certainly the most common method, it is not appropriate for all types of semiconductor failure analysis. Contaminants on the surface of the semiconductor die can be washed away by the acids and solvents; if the contaminants had no secondary effect (for example, corrosion of the traces on the IC), there will often be no remaining clue as to the root cause of failure on the device. If something in the failure characteristics or device history suggests that contamination might be present, a different decapsulation approach is necessary. For plastic encapsulated devices, one such method is plasma etching. The sample is placed in a tool capable of generating a reactive plasma - a reactive ion etcher is the most likely candidate, since the FA lab is likely to have one already to support deprocessing work - and exposed to pure oxygen gas. The plasma oxidizes the plastic mold compound, turning it into a fine ash that can be easily cleaned away, eventually revealing the die. Many contaminants that might lead to a failure - halides, metal particulate, and others - do not react with this oxygen plasma, or react at a much slower rate, and so are left behind by the ashing process.
The assumption in both wet IC decapsulation and plasma etching as described above is that a semiconductor is encased in a plastic mold compound; for devices in ceramic cases, embedded in other types of materials, or mounted in other unusual ways (for example, many mobile devices mount the semiconductor die as a flip chip directly onto the printed circuit board, forgoing traditional packaging altogether), other techniques must be developed and deployed. A certain degree of creative latitude is necessary
Derek Snider is a failure analysis engineer at Insight Analytical Labs, where he has worked since 2004. He received his Bachelor’s of Science in Electrical Engineering from the University of Colorado at Colorado Springs.