As with any project, the ultimate goal in capacitor failure analysis is determining a root cause for failure - in other words, finding whether the improper operation is due to manufacturing imperfections, end-user abuse, or other factors. Just as with an integrated circuit, the first step in the process is determining where an analyst should even begin looking for a failure; after all, failing capacitors rarely give outward indication that they have malfunctioned (though an exception can be found with polarized electrolytic capacitors, which have a tendency to explode violently when abused, much to the chagrin of many an inattentive engineering student). The same set of tools that an analyst uses to ferret out defects on an integrated circuit can also be applied to the analysis of a capacitor, with the addition of a little creativity.
The most common failure mechanism for capacitors is a compromised dielectric causing leakage between the capacitor’s two electrodes. Depending on the type of capacitor, this dielectric may take many forms; one of the most common capacitors, the multi-layer ceramic capacitor often referred to as a chip cap, uses a ceramic material comprised of small particles of various materials blended to achieve a desired set of characteristics. In this type of capacitor, the most common failure is cracking or delamination of the capacitor’s internal layers. An acoustic microscope can be used to detect these damaged dielectrics, just as it might find delamination in an encapsulated integrated circuit; analyzing a capacitor acoustically, however, does not necessarily follow the same course as analyzing a packaged IC.
In a packaged IC, there are two primary acoustic techniques for determining the condition of a package; a plan-view image of the device (referred to as a C-Mode image), and comparisons of the reflected acoustic wave at several points (known as A-Scans). The C-Mode image contains data about a small handful of interfaces within the package (e.g. the die-to-encapsulant interface, or the encapsulant-to-leadframe interface), while variations in phase and amplitude on the A-Scan can be used to identify differences between points that might indicate a defect. A chip cap has many more interfaces than an integrated circuit, with multiple layers of metal and ceramic stacked upon one another; the C-Scan can really only be used to look at one of these interfaces at a time, and as such is not an ideal approach to analyzing the entire device. For a ceramic capacitor, the appropriate technique is a tomographic approach known as a B-Scan - a technique which provides cross-sectional images of the entire thickness of the device.
Using a B-Scan, it is not only to determine the presence of a damaged dielectric in the capacitor, but also its relative location in the device, facilitating a targeted cross-section. Since many capacitor failures result in increased leakage current, many integrated circuit techniques for isolating leakage translate directly to capacitor analysis. While techniques steeped in semiconductor physics like photoemission are of limited utility for capacitor failure analysis, methods of isolating current flow by its secondary effects, like thermal imaging, are more than capable of identifying dielectric pinholes or other leakage sites.
Since these techniques often rely on line-of-sight, they are more useful as a secondary confirmation of a failure, correlating an electrical signature to a physical defect revealed during deconstruction or cross-section of a device. The failures here are only a small incursion into the realm of capacitor failure analysis. Indeed, even devices as seemingly humdrum as the simple capacitor can make for exciting failures; leaking electrolytic capacitors may cause catastrophic failure in the form of burnt circuit boards, tantalum capacitors may explode in a shower of sparks, and high voltage capacitors may break down with a thunderous crack. Despite their simplicity, failure analysis on capacitors is a complex, yet worthwhile endeavor, even if the end result is only an improvement in product reliability instead of the aversion of an uncontrollable conflagration.