Our Staff

Thomas E. Paquette

President

Mr. Thomas Paquette's strong engineering background, combined with his broad business management experience, provides a unique customer-focused perspective. Tom is able to define complex technical issues, follow problems to root causes, and propose and implement innovative, yet pragmatic, solutions within rapidly changing markets. These abilities have consistently enhanced the organization's competitive positions.

Following his graduation from Clarkson University with a BSEE, Mr. Paquette joined the IIT Research Institute as a consultant. Upon completion of that DoD assignment, he held positions of increasing responsibility within Mostek, Honeywell, United Technologies, and Ford Microelectronics. In each environment, he was a key figure in establishing reliability and failure analysis facilities, designing reliability structures for both GaAs processes and printed circuit boards, setting industry standards for latch-up stressing, and influencing ESD standardization.

While at Ford Microelectronics from 1984 to 1995, Mr. Paquette led a group that supported Ford Motor Company's design innovations; the group later became recognized as a world leader in IDDq testing and implementation. Mr. Paquette was also responsible for assessing new IC technologies, improving ESD performance, establishing road maps for implementation of 3.3 volt ICs, improving board-level reliability, consulting on qualification specifications, and supporting Ford's development efforts in fine-pitch and multi-chip packaging (a report on MCMs was presented at the Colorado Springs IEEE).

Mr. Paquette's commitment to the industry has been demonstrated through his involvement and leadership roles in professional organizations. Tom is a member of IEEE, has been a major contributor to the JEDEC Standards Committee and has been a founding member of several corporate standards alliances. He has also been a member of the Technical Committee for the International Reliability Physics Symposium, and he co-presented an IDDq testing and implementation workshop at the 1995 IRPS. Tom also presented a short course on future reliability concerns at the 1998 UC Berkeley extension course in Colorado Springs. In the past few years, Tom has presented several seminars on WLR, dielectric reliability, and failure analysis both in Europe and Asia.

Mr. Paquette is the company's founder and currently functions as president of Insight Analytical Labs. The company's mission is to identify and recommend corrective actions for electronic product manufacturing and reliability problems.

Pamela J Ritter

Vice President of Marketing/Sales and Quality Manager

Mrs. Ritter joined Insight Analytical Labs in October of 1995. She has an Associates of Applied Science Degree in Computer Networking along with an Associate of Applied Science Degree in Computer Information Systems.

While at IAL, she has been a part of the office staff as the Executive Assistant and the IT manager. Pam has also assisted the technical staff working with general F/A procedures, with an emphasis on Acoustic Microscopy. 

Mrs.Ritter's current position is Vice President of Marketing/Sales, and Quality Manager which utilizes her work experience in the different areas of the lab. As the Vice President of Marketing/Sales and the Quality Manager, Pam's responsibilities include:

• Implementing and enforcing the operating procedures to ensure a quality product,the safety of the employees, and the protection of IAL's assets in an efficient and effective manner.
• Maintaining the ISO certification.
• Quoting.
• Customer Visits
• Sales
• Coordinating with customers on complaint resolution.
• Qualifying and disqualifying IALs suppliers.
• Maintaining the Qualified Suppliers List.
• Coordinating audits of each of the operating areas within IAL.

Mrs. Ritter played a important role in helping Insight Analytical Labs, achieve and maintain their current ISO certification.

Mrs. Ritter also manages the Local Area Network, the information technologies of IAL to include the implementation of new equipment and applications.

Gary Shade
Sr. Staff Engineer and Project Manager

Gary joined IAL in 2006 as a Senior Staff Engineer. He has 29 years experience in the semiconductor industry.  He started his career as a Research Associate in semiconductor epitaxial growth and sub-micron GaAs wafer processing for both analog microwave and leading edge digital products.  With his broad process background, Gary turned to Failure Analysis in 1988 and found his true passion.  He joined the ISTFA Organizing committee where he has held every post and recently completed his term as Society president of EDFAS, the society for FA professionals.   He has also led the Automotive Reliability Workshop and worked on analog and digital GaAs, Automotive ICs for Ford Motor, MEMS, and Leading edge ICs for Intel.  He is familiar with all aspects of FA including new technique and tool development, and has contributed several papers and two invited tutorials to ISTFA.  He holds two patents; one for analog GaAs and one for MEMs.  Gary has taught classes on device physics and photoemission for undergraduate and graduate university students.  He has also served as an expert witness on Photoemission Microscopy.

Gary's current position at IAL is Sr. Staff Engineer and Project Manager, which allows him to practice hands-on FA while developing new techniques and assist in training.  His specialties include:

• Theory and application of photoemission microscopy.
• Device Physics
• FA method and techniques
• Metrology and tool development   

Gary graduated from Wm. Jewell College with a degree in Physics.  He continued his education at Washington University in St. Louis finishing with a BS/MS EE in device physics for analog and optoelectronic devices.

Heidi M. Bates
Failure Analysis Engineer and Lead Project Manager

Ms. Bates joined Insight Analytical Labs at the beginning of 1997 following her work in the semiconductor gas purification field.  Her previous experience includes extensive work with an Atmospheric Pressure Ionization Mass Spectrometer and various other gas analysis instruments. 

Currently, Heidi functions as a Failure Analysis Engineer and Lead Project Manager with emphasis on acoustic microscopy die cross-sectioning, and failure analysis.  Using her chemical background, Heidi has helped develop staining techniques for destructive physical analysisof state-of-the-art integrated circuits.  With the use of multiple techniques, she has been able to identify problems with package design and die attach.  As a Project Lead and Failure Analysis Engineer Heidi's responsibilities include

• Working directly with customers
• Decapsulation and depotting of plastic IC’s
• Cross-sectioning
• SEM inspection
• Chemical deprocessing
• Parallel lapping
• EDS analysis

With her responsibility for acoustic microscopy at IAL, Heidi is developing new applications as well as supporting customers in determining the best techniques to resolve their problems.

Steve A. Reynoso
Failure Analysis Engineer and Project Manager

Steve is a Project Manager and Failure Analysis Engineer with over 25 years of experience in electronic systems and semiconductors.  He has extensive knowledge of failure analysis and reliability studies for ASIC and standard ICs.  Steve has semiconductor experience from Motorola, IBM, Litton Data Systems, Ford Microelectronics, and Intel.

As a Project Lead and Failure Analysis Engineer Steve’s responsibilities include

• Destructive physical analysis such as: decapsulation and depotting of         plastic encapsulated IC’s, cross sectioning and staining cross sectioned parts to identify manufacturing defects.
• Microprobing of ICs for electrical testing, fault isolation, and failure mode recreation.
• Infrared Microscopy and liquid crystal techniques for identifying failing locations.
• High resolution X-Ray
• Energy dispersive spectroscopy (EDS) using IAL’s state of the art EDAX   EDS to perform quantitative material composition analysis.
• Light Emission Microscopy.
• Electrical testing using the curve tracer and bench top equipment.
• The use of wet chemical and dry plasma etching techniques to identify integrated circuit defects.

Steve has a broad knowledge of generating qualification plans, performing reliability stress testing, ESD evaluations, designing dynamic burn-in, Life -Test, and HAST bias diagrams.  Steve graduated with a BSCE from Colorado Technical University.  He is a former JEDEC and EOS/ESD Association committee member.  Steve is a member of the IEEE and is an ITSFA, IPC APEX, and IRPS attendee.