Dual-Beam FIB

Overview

The greatest challenge a failure analyst faces on a day-to-day basis is the ever-changing nature of semiconductor technology. Even if alternative processes like silicon-on-insulator or III-V semiconductors are not considered, the CMOS transistor of today is, quite literally, a shadow of its former self; modern transistors are fabricated with gate lengths as short as 22 nanometers, meaning that only a few hundred silicon atoms separate the source and drain of a cutting-edge transistor. This miniaturization means that many standard methods in the F/A toolbox lack the precision and resolution necessary to properly work with modern technologies; the Dual-Beam FIB, however, can extend those capabilities, allowing the analyst to work with even the most cutting-edge parts.

Fundamentals

A Dual-Beam FIB combines a high resolution Field Emission Scanning Electron Microscope (FESEM) with a Focused Ion Beam (FIB), which uses a beam of charged gallium atoms to generate images. Since a gallium atom has much more mass than an electron, the FIB can actually be used as a sort of precision ballistic mill, slowly removing material wherever it is aimed - think of an extremely small, highly focused sandblaster. The FIB can therefore be used to perform precisely targeted cross-sections of a device (for example, sectioning a single failing memory bit). Furthermore, the electron and ion beams are configured such that electron images of the cross-section face can be obtained while polishing with the ion beam, making it easy to identify when the feature of interest has been exposed.

  • Plan-View STEM image of a polysilicon device
    Plan-View STEM image of a polysilicon device
  • Probe crosses added with FIB microsurgery
    Probe crosses added with FIB microsurgery
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    A "Stained-Glass" TEM lamella, showing the grain structure of a copper metal bus
  • Cross-section of an integrated circuit performed with FIB
    Cross-section of an integrated circuit performed with FIB
  • A TEM lamella being lifted away from the integrated circuit from which it was carved
    A TEM lamella being lifted away from the integrated circuit from which it was carved
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The Dual-Beam is also used to prepare samples for transmission electron microscopy (TEM) inspection. TEM is much higher resolution than SEM, with the most advanced tools boasting resolution high enough to image individual atoms; the drawback to these tools, however, is that they require extensive sample preparation. A TEM sample must be polished to a thickness of 100 nanometers or less, to allow the electron beam to completely pass through the sample. The FIB incorporates a nanoprobe system to make this process fairly straightforward; a sample can be prepared either cross-sectionally or as a plan-view sample, lifted out, and mounted on a grid for TEM inspection all without breaking vacuum on the chamber. The Dual-Beam also incorporates a scanning TEM (STEM) detector, offering much higher resolution images than SEM, if not the atomic-scale resolution provided by TEM.

By combining the energy from the ion beam with certain reactant gasses, the FIB can also be used as a selective etching or metal deposition tool. This allows the Dual-Beam to perform some limited circuit edit functions, removing oxides or cutting and rewiring the traces on an integrated circuit to troubleshoot designs or isolate nodes for failure analysis.

Sample Types

The Dual-Beam has a relatively large chamber, and can accept almost any packaged IC, wafers (6” or less preferred), and small circuit boards. Conductive samples provide the best results; non-conductive samples will generally be sputtered with either a gold-palladium alloy or iridium to mitigate any charging effects.

Applications

  • Construction analysis of an integrated circuit
  • Performing multiple cross-sections and images through a region of interest for failure analysis
  • Examining polycrystalline grain size and structure
  • Design debugging

Limitations

Cross-sectioning, TEM preparation, and STEM imaging are possible with a high success rate on practically any integrated circuit, including even the most cutting edge alternative CMOS processes like FINFETs. Circuit edit capabilities are more limited; basic cutting, deposition of probe pads, and creating short jumpers between metal lines is possible, but as the complexity of the device and the desired edit increases, the likelihood of success goes down.

 

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