Although IAL was started by Tom Paquette, it has been the addition of its key people, their talents and dedication, which have made it so successful in so few years. Your business will benefit from the extensive knowledge and experience of our staff. We have experts in wafer processing, failure analysis experience, acoustic microscopy, wafer fabrication, quick-turn package decapsulation, X-ray fluorescence, and other services. IAL staff has over 150 years of electronic failure analysis experience. As our customer, you have direct access to the technical person performing the analysis for you.
Mr. Thomas Paquette's strong engineering background, combined with his broad business management experience, provides a unique customer-focused perspective. Tom is able to define complex technical issues, follow problems to root causes, and propose and implement innovative, yet pragmatic, solutions within rapidly changing markets. These abilities have consistently enhanced the organization's competitive positions.
Following his graduation from Clarkson University with a BSEE, Mr. Paquette joined the IIT Research Institute as a consultant. Upon completion of that DoD assignment, he held positions of increasing responsibility within Mostek, Honeywell, United Technologies, and Ford Microelectronics. In each environment, he was a key figure in establishing reliability and failure analysis facilities, designing reliability structures for both GaAs processes and printed circuit boards, setting industry standards for latch-up stressing, and influencing ESD standardization.
Ms. Bates joined Insight Analytical Labs at the beginning of 1997 following her work in the semiconductor gas purification field. Her previous experience includes extensive work with an Atmospheric Pressure Ionization Mass Spectrometer and various other gas analysis instruments.
Currently, Heidi functions as a Failure Analysis Engineer and Lead Project Manager with emphasis on acoustic microscopy die cross-sectioning, and failure analysis. Using her chemical background, Heidi has helped develop staining techniques for destructive physical analysisof state-of-the-art integrated circuits. With the use of multiple techniques, she has been able to identify problems with package design and die attach. As a Project Lead and Failure Analysis Engineer Heidi's responsibilities include:
Gary joined IAL in 2006 as a Senior Staff Engineer. He has 29 years experience in the semiconductor industry. He started his career as a Research Associate in semiconductor epitaxial growth and sub-micron GaAs wafer processing for both analog microwave and leading edge digital products. With his broad process background, Gary turned to Failure Analysis in 1988 and found his true passion. He joined the ISTFA Organizing committee where he has held every post and recently completed his term as Society president of EDFAS, the society for FA professionals. He has also led the Automotive Reliability Workshop and worked on analog and digital GaAs, Automotive ICs for Ford Motor, MEMS, and Leading edge ICs for Intel. He is familiar with all aspects of FA including new technique and tool development, and has contributed several papers and two invited tutorials to ISTFA. He holds two patents; one for analog GaAs and one for MEMs. Gary has taught classes on device physics and photoemission for undergraduate and graduate university students. He has also served as an expert witness on Photoemission Microscopy.
Michael joined IAL in 2010 as a Failure Analysis Engineer. At the time that he joined IAL he had 11 years of diversified experience in the semiconductor industry, holding positions in process manufacturing and yield enhancement, product marketing, and business development.
Michael had a primary role in the development and integration of Atmel’s 50GHz BiCMOS processes. Michael also managed product planning and development for Atmel’s wireless connectivity products. He has contributed several whitepapers on advanced wireless products for 3G and 4G networking that have been featured in IEEE magazines worldwide.
Chris has over 35 years experience in the semiconductor industry. He started his career at Texas Instruments as a Failure Analyst, and failure analysis has bee his passion ever since. Chris’s broad range of experience in the semiconductor industry has provided expertise in all areas of Failure Analysis. His experience ranges from I/C Designer, Product Engineer, Process Integration Engineer, Yield Engineer, Reliability Engineer, and QA Engineer. Chris has been a key contributor in new product introduction for designs using new technology for Vitesse and Cypress. Chris has worked with many of the design and process technologies in his career. Some of his experiences in the design and process technologies are dynamic and static RAM, EPROM, Microprocessors, Linear products, Metal Gate, CMOS, VMOS, Bipolar (including schottky design), CMOS (including radiation harden technology), Silicon On Insulator (SOI), and GaAs technology.